1. Field of the Invention
The present invention relates to an IC (Integrated Circuit) card and a method for parallel processing flash memories. In particular, the present invention relates to a method for performing parallel writing and parallel erasing for a plurality of flash memories incorporated in an IC card, and the configuration of such an IC card.
2. Description of the Related Art
In recent years, it has become popular to access information by utilizing IC cards. Access to the information in an IC card by a personal computer can be made by, as shown in FIG. 17 for example, attaching the IC card 10 to a main body 2 of a personal computer 1, and operating a keyboard 3 connected the main body 2 via a cable 4. Thus, the information stored in the IC card 10 can be accessed (read/written) by the computer 1, and results of operations made by the computer 1 can be stored in the IC card 10.
FIG. 18A shows the structure of a portion of the computer main body 2 at which the IC card 10 is connected. FIG. 18B shows the internal structure of the IC card 10. As shown in FIG. 18A, a card socket 5 installed inside the computer main body 2 interconnects an operation device (not shown) of the computer 1 to the IC card 10. The card socket 5 has a structure capable of holding the IC card 10 in place. Connection pins 5a, which are connected to the operation device via wires 5b, are provided in a portion of the card socket 5. When the IC card 10 is inserted in the card socket 5, the connection pins 5a are electrically connected to connection terminals 21 of a connector portion 20 of the IC card 10.
The IC card 10 includes, for example, a signal processing device and/or a storage device provided on a card substrate 30 such as a printed circuit board. To one end of the card substrate 30 of the IC card 10, the connector portion 20 is attached. Thereafter, the entire card substrate 30 is sealed with a packaging member 10a such as a resin film. As a signal processing device, a card interface 50 is mounted on the card substrate 30. The card interface 50 processes a plurality of input signals and output signals. As storage devices, a plurality of flash memories 40a to 40d are mounted on the card substrate 30. On one end of the card substrate 30, a plurality of connection terminals 31, which are connected to the respective connection terminals 21 of the connector portion 20, are provided so as to be aligned along the end.
FIG. 19 is a diagram showing the flow of signals between the card connector 20, the card interface 50, and the flash memories 40a to 40d. FIG. 20 is a diagram showing the internal configuration of the card interface 50.
As best seen in FIG. 20, the card interface 50 is coupled to the card connector 20 via an input/output buffer 51, and to the flash memories 40a to 40d via an input/output buffer 55 in the card interface 50. In other words, access to data signals D0 to D15 between the card interface 50 and the card connector 20 is made via the input/output buffer 51; access to data signals D0 to D7 between the card interface 50 and the flash memories 40a and 40c is made via the input/output buffer 55; and access to data signals D8 to D15 between the card interface 50 and the flash memories 40b and 40d is made via the input/output buffer 55. The card interface 50 includes a data control 54 for varying a bus width, which is the reason why a 16-bit data bus is employed between the input/output buffer 51 and the data control 54, and two 8-bit data buses are employed between the input/output buffer 55 and the data control 54. The data bus for transmitting the data signals D0 to D7 is shared by the flash memories 40a and 40c. The data bus for transmitting the data signals D8 to D15 is shared by the flash memories 40b and 40d.
In the descriptions of various signals in the rest of the present specification, the symbol "/" is conveniently used to express " " (bar). For example, "/AB" represents "AB", and "AB//CD" represents "AB/CD", while "AB/CD" should simply be interpreted as "AB/CD".
The card interface 50 further includes an input buffer 52 for receiving address signals A0 to A21, chip enable signals /CE1 and /CE2, a write enable signal /WE, and an output enable signal /0E. All the address signals A0 to A21 except for the most significant decode address signals A20 and A21, i.e., the address signals A0 to A19, are supplied to the flash memories 40a to 40d via the output buffer 56a. Furthermore, the card interface 50 includes a controller 53 for controlling the flash memories 40a to 40d and the data bus control 54 based on the chip enable signals /CE1 and /CE2, the write enable signal /WE, the output enable signal /0E, and the most significant decode address signals A20 and A21.
The controller 53 selects one of the flash memories 40a to 40d in accordance with chip select signals /CS0 and /CS1, which are based on the most significant decode address signals A20 and A21. The controller 53 generates write enable signals /WE0 and /WE1 based on the chip enable signals /CE1 and /CE2 and the write enable signal /WE, and selects the one of the flash memories 40a to 40d in which information is to be written, based on the generated write enable signals /WE0 and WE1. Thus, the controller 53 functions to supply the output enable signal /0E from the input buffer 52 to the flash memories 40a to 40d. Since the IC card 10 of this example has only four flash memories 40a to 40d, it is not necessary to employ chip select signals /CS2 to /CS7.
The card interface 50 includes an input buffer 58 for receiving ready busy signals R/B0 to R/B3 from the flash memories 40a to 40d, a signal processing circuit 59, and an output buffer 57. The signal processing circuit 59 outputs a ready busy signal RDY//BSY which is at an L (low) level when one of the ready busy signals R/B0 to R/B3 is at the L level, and subjects the output from the input buffer 58 to a signal process. The output buffer 57 outputs the ready busy signal RDY//BSY to the card connector 20.
Furthermore, the card socket 5 supplies a voltage Vcc for driving the flash memories 40a to 40d and supply voltages Vpp1 and Vpp2 for writing operations and erasing operations to the IC card 10. The supply voltage Vpp1 is coupled to the flash memories 40a and 40c in the first row, which is for even-numbered bytes. The supply voltage Vpp2 is coupled to the flash memories 40b and 40d in the second row, which is for odd-numbered bytes. Signals /CD1 and /CD2, which are supplied to the card connector 20 as ground voltages, are employed for determining whether the IC card 10 is properly connected to the card socket 5. When the connection between the IC card 10 and the card socket 5 is incomplete, the computer 1 terminates any processing for the IC card 10.
In the IC card 10 of the above-described configuration, the data bus and the address buses, except for those which correspond to the most significant decode address signals A20 and A21, are shared by a plurality of flash memories. A reading operation, a writing operation, or an erasing operation is performed by accessing one of the flash memories based on the most significant decode address signals A20 and A21 and the chip enable signals /CE1 and /CE2.
For example, in the case where the flash memory 40c is selected, the decode address signal A20 and A21 and the chip enable signals /CE1 and /CE2 are first varied in such a manner that the chip select signal /CS0 is at the L (low) level and that the chip select signal /CS1 is at an H (high) level. As a result, the flash memories 40c and 40d aligned in a horizontal row in FIG. 19 are selected.
When the card interface 50 outputs the write enable signal /WE0 at the L level and the write enable signal /WE1 at the H level based on the chip enable signals /CE1 and /CE2 and the write enable signal /WE, for example, the flash memories 40a and 40c aligned in a vertical row in FIG. 19 are selected. As a result, the flash memory 40c is selected.
The IC card 10 carrying the flash memories 40a to 40d mounted thereon must be subjected to a test with respect to each memory after the flash memories 40a to 40d are mounted on the card substrate 30. The reason is that, although a device test is expected to have been conducted for each flash memory before it is mounted, there is a possibility for one or more of the flash memories to have defective portions while being mounted on the card substrate 30.
Japanese Laid-Open Patent Publication No. 2-148500 describes an example of a method for performing such a device test. According to this method, when writing or erasing information in a flash memory of an IC card, a write command or an erase command, an address signal,and data are supplied from a connector of the IC card, and one of the flash memory devices is selected via a card interface, whereby access is made.
The outline of such a test method will be described below.
FIG. 21 schematically shows the configuration of an apparatus to be used for conducting a test for an IC card before being sealed with a packaging member. FIG. 22 shows the flow of a signal from a card connector 62 used in this test apparatus (hereinafter referred to as "test card connector") to the inside of the IC card.
Necessary devices such as a card interface 50 and flash memories 40a to 40d are already mounted on the card substrate 30. The test apparatus 60 includes a main body 60a for performing a signal process for test signals and a support 60b for the card substrate 30 carrying the flash memories 40a to 40d. The support 60b includes a base 61 for supporting the card substrate 30 and the test card connector 62 for applying test signals to connection terminals 31 of the IC card 10. As shown in FIG. 22, the test card connector 62 has a configuration corresponding to that of the card socket 5 incorporated in office automation equipment, e.g., personal computers.
FIG. 23 shows the flow of a writing test. FIG. 24 shows the flow of an erasing test. Two methods are applicable to these tests: a byte (8 bit) access method and a word (16 bit) access method. Under the byte (8 bit) access method, access is made to every device (flash memory) in a serial manner, and the test is repeated as many times as the number of devices. Under the word (16 bit) access method, access is made to every pair of devices (two flash memories), and the test is repeated as many times as the number of pairs of devices. The flows shown in FIGS. 23 and 24 correspond to the byte access method.
Hereinafter, the writing test will be described.
At step Sr1, the first test device is selected based on the most significant decode address signals A20 and A21 and the chip enable signals /CE1 and /CE2. For example, the flash memory 40c may be selected. Thereafter, a write setup command is supplied to the flash memory 40c. As a result, the flash memory 40c enters a write enabled state (step S11). Next, a write command is supplied to the flash memory 40c (step S12). Furthermore, a write address and data are supplied to the flash memory 40c, and test data is written in a predetermined address of the flash memory 40c (step S13). Thereafter, it is determined whether or not the test data is properly written in the address (step S14).
If a write error is detected, the writing test for the flash memory 40c is finished. If no write error is detected, it is determined whether or not the address for which the above-mentioned writing has been conducted is the last address (step S15). If the address is not the last address, the process goes back to step S12. When the writing judgment is complete for every address of the flash memory 40c, the writing test for the first flash memory 40c is finished. The writing judgment process (steps S11 to S15) is repeated for the other flash memories 40a, 40b, and 40d provided on the card substrate 30. In other words, steps Sr2 to Sr4 are performed, and the overall writing test for the IC card 10 is finished.
In this example, the number of flash memories mounted on the card substrate 30 is four, so the above-described writing judgment process is conducted four times. However, it will be appreciated that the writing judgment process is conducted as many steps Srn as the number n of the flash memories mounted on the card substrate 30.
Next, the erasing test will be described. The erasing test is performed in substantially the same manner as the writing test. Specifically, at step Se1, the first test device is selected, e.g., the flash memory 40c. Thereafter, an erase setup command is executed, whereby the flash memory 40c enters an erasable state (step S21). Next, a block of the flash memory 40c that is to be erased is designated (step S22). Then, an erase command is executed so as to erase information stored in the addresses of the designated block (step S23). Thereafter, it is determined whether or not the data in the addresses of the designated block is properly erased (step S24). If an erase error is detected, the erasing test for the flash memory 40c is finished. If no erase error is detected, it is determined whether or not the block for which the above-mentioned erasing has been conducted is the last block (step S25). If the block is not the last block, the process goes back to step S22. When the erasing judgment is complete for every block, the erasing test for the first flash memory 40c is finished. The erasing judgment process (steps S21 to S25) is repeated for the other flash memories 40a, 40b, and 40d provided on the card substrate 30. In other words, steps Sr2 to Sr4 are performed, and the overall erasing test for the IC card 10 is finished.
Although a writing test and an erasing test by the byte access method were described, where the flash memories 40a to 40d were individually tested, access to the flash memories 40a to 40d may be made by the word access method, where each process in the writing test (steps S11 to S15) and each process in the erasing test (steps S21 to S25) can be performed for every two flash memories. By thus adopting the word access method for the writing test and erasing test, each process need only be repeated half the number of times as the number of flash memories mounted on the card substrate 30.
The time required to perform a writing process or an erase process for all the flash memories in the IC card 10 by the byte access method is: (the time required for writing or erasing information in one flash memory).times.(the number of device). By the word access, it is: (the time required for writing or erasing information in one pair of flash memories).times.(the number of pairs of devices).
Currently, an 8M-bit IC card manufactured by Sharp Kabushiki Kaisha., i.e., an IC card in which 8M-bit flash memories are mounted, takes one second or less to read all the addresses of one flash memory, 9.6 seconds to write in all the addresses of one flash memory, and 25.6 seconds to erase from all the addresses of one flash memory. These time values are taken under a standard operation.
Accordingly, a 4M-byte IC card, i.e., an IC card in which four 8M-bit flash memories are mounted, takes 38.4 seconds (=9.6.times.4) to write, and 102.4 seconds (=25.6.times.4) to erase, by the byte access method. The 32-byte IC card takes 19.2 seconds (=9.6.times.2) to write, and 51.2 seconds (=25.6.times.2) to erase, by the word access method.
The number of devices, i.e., flash memories, to be mounted in an IC card is expected to increase as the high-density mounting technique for IC cards improves. The time required for the writing processes and the erasing processes in the conventional test methods drastically increases in proportion with the number of devices, thereby greatly increasing the cost of examination for the IC card. It is difficult to realize parallel writing or parallel erasing by using a testing program, too.